The present invention relates to a liquid crystal display device and, more particularly, to a technique effective in lowering the power consumption of a liquid crystal display device to be incorporated in a portable information terminal or the like.
An STN (Super Twisted Nematic) type simple matrix liquid crystal display device has been widely used as a display device for a notebook personal computer or the like. FIG. 5 is a schematic block diagram showing a typical example of the construction of such an STN type simple matrix liquid crystal display device. In FIG. 5, reference numeral 101 designates a display control unit, reference numeral 102 designates a power supply circuit, and symbol LCD denotes a liquid crystal display panel.
The liquid crystal display panel LCD is equipped with a pair of glass substrates mutually opposed and arranged on either side of a liquid crystal. On the face of one glass substrate on the liquid crystal side, there are formed m common electrodes (or scanning lines) which extend in an X-direction, are juxtaposed in a Y-direction and are connected with corresponding common drivers (IC-C 1 to IC-C5). On the face of the other glass substrate on the liquid crystal side, there are formed n segment electrodes (data lines) which extend in an X-direction, are juxtaposed in an X-direction and are vertically grouped into two groups. These n segment electrodes of two groups are connected with either the upper corresponding segment drivers (IC-U1 to IC-Un) or the lower corresponding segment drivers (IC-L1 to IC-Ln). The intersections between the segment electrodes and the common electrodes constitute pixel regions, the pixels of which are driven by applying drive voltages from the upper segment drivers (IC-U1 to IC-Un), the lower segment drivers (IC-L1 to IC-Ln) and the common drivers (IC-C1 to IC-C5) to the segment electrodes and the common electrodes.
In FIG. 5, the liquid crystal panel control unit 101 controls the segment drivers (IC-U1 to IC-Un and IC-L1 to IC-Ln) and the common drivers (IC-C1 to IC-C5) on the basis of display control signals, transferred from a host computer or the like, and the display data. The power supply circuit 102 generates data signal line drive voltages VH, VM and VL, scanning line signal drive voltages VxH, VxL, Vcc and GND and feeds the voltages VH, VM, VL, Vcc and GND to the segment drivers (IC-U1 to IC-Ln) and the voltages VxH, VM, VxL, Vcc and GND to the common drivers (IC-C1 to IC-C5). In a simple matrix type liquid crystal display device, it is known to use a so-called current-alternating drive method, in which the drive voltages to be applied to the segment electrodes and the common electrodes are inverted for a predetermined period so that a DC voltage will not be applied to the liquid crystals.
FIG. 6 is a diagram for explaining one example of the data signal line drive voltages to be applied to the segment electrodes of the liquid crystal panel LCD shown in FIG. 5, and the scanning line signal drive voltages to be applied to the common electrodes. In the example shown in FIG. 6, when the current-alternating signal M is at a high level, the drive voltage VL is fed to the segment electrodes of display data "1" from the power supply circuit 102, and the drive voltage VH is fed and applied to the segment electrodes of data "0" from the power supply circuit 102. Likewise, when the current-alternating signal M is at a low level, the drive voltage VxH to be fed from the power supply circuit 102 is applied to the selected common electrodes. When the current-alternating signal M is at the high level, the drive voltage VxL to be fed from the power supply circuit 102 is applied to the selected common electrodes. Whether the current-alternating signal M is at the high or low level, the drive voltage VM to be fed from the power supply circuit 102 is applied to the nonselected common electrodes.
FIG. 3 is a block diagram of the segment driver of the display device shown in FIG. 5. The segment driver shown in FIG. 3 is constructed of a shift register circuit 301, a bit latch circuit 302, a line latch circuit 303, an output circuit 304 and a random logic circuit 310. Here, this random logic circuit 310 is equipped with a standby circuit 307 for bringing one segment driver into a standby state when no data latch is required. Numeral 308 designates an EIO1 circuit, and numeral 309 designates an EIO2 circuit. These EIO1 and EIO2 circuits receive a carry signal from the segment driver of the preceding stage, and output internal carry signals CAR1 and CAR2 to the shift register circuit 301 and a standby signal STBY to the standby circuit 307, as well as a carry signal to the next-stage segment driver. FIG. 3 shows a segment driver having two hundred and forty outputs, and symbols Y1 to Y240 designate the output terminals.
Now, the data fetching and outputting operations of the segment driver shown in FIG. 3 will be described. In the random logic circuit 310, a display data latching clock signal CL2 inputted from the display control unit 101 is converted into an internal data latching clock signal SCL2. On the basis of this internal data latching clock signal SCL2, the shift register circuit 301 generates a data fetching signal for latching data in the bit latch circuit 302 and outputs it to the bit latch circuit 302. Moreover, 4-bit display data DATA inputted from the display control unit 101 is also converted into internal data SD. The internal data latching clock signal SCL2 and the internal data SD is fixed to the low level when in the standby state. The bit latch circuit 302 latches the internal data SD on the basis of the data fetching signal inputted from the shift register 301.
On the basis of an output timing controlling line clock signal CL1, although not shown, the line latch circuit 303 latches the display data fetched by all the bit latch circuits 302, and outputs this data to the output circuit 304. The output circuit 304 converts the voltage level of the display data inputted from the line latch circuit 303 to a high voltage level, and performs the aforementioned current-alternating operations from the data converted into the high-voltage level and the current-alternating signal M so as to select one of the three-level data signal line drive voltages fed from the power supply circuit 102, thereby to output the selected three-level data signal line drive voltage to the segment electrodes (data signal lines).
FIG. 7 shows an operating state diagram of the segment drivers for each period when one-line of data is written. In FIG. 7, the display data for one line juxtaposed in the X-direction is outputted from the n segment drivers. In this case, the segment drivers (IC-U1 to IC-Un and IC-L1 to IC-Ln) start operating according to a later-described carry signal (bar EIO1 or bar EIO2) to fetch display data at that time. The segment drivers (IC-U1 to IC-Un, and IC-L1 to IC-Ln) to which the carry signal is not inputted are held in a standby state in which their internal operations are stopped, because they need not fetch the display data. The segment drivers (IC-U1 to IC-Un and IC-L1 to IC-Ln) having finished the fetching of the display data stop their internal operations to take up the standby state. As a result, in the prior art, the segment drivers (IC-U1 to IC-Un and ICL1 to IC-Ln) are brought one by one into the standby state to lower the power consumption.
FIG. 4 is a timing chart for the segment drivers and shows the carry signal (bar EIO1 or bar EIO2) and the operations in the segment drivers. FIG. 4 shows an example in which the data fetching signals are shifted from the left to the right in the shift register 301 shown in FIG. 3. As a result, the carry signal bar EIO1 is inputted, and the carry signal bar EIO2 is outputted and inputted to the carry input of the next-stage segment drivers (IC-U1 to IC-Un and IC-L1 to IC-Ln). The inside of the segment driver is divided into internal circuits, as shown in FIG. 3, so that the operations are started in all the circuits simultaneously with the input of the carry signal bar EIO1 and all lines of the internal data bus SD and the data latching clock signal SCL2 in the segment drivers are activated.
In the prior art thus far described, the standby state is controlled only in units of one segment driver, so that the control is insufficient to lower the power consumption.